Davicom DM9102HEP 10/100Mbps Fast Ethernet MAC Single Chip Fast Ethernet NIC Controller

Davicom

DM9102HEP

MII, PCI Interface, PHY

SMT

25+

Taiwan, China

Network Interface Adapter, Surveillance Camera, Embedded System, Ethernet Hub, Ethernet Switch

PHY, MAC

DM9102H seriers

The DM9102H is a fully integrated and cost effective singlechip Fast Ethernet NIC controller. It is designed with lowpower and high performance process. It is a 1.8V/3.3Vdevice with 5V tolerance.The DM9102H provides direct interface to the PCI bus andsupports bus master mode to achieve the high performanceof the PCI bus. It fully complies with PCI 2.2. In the mediaside, the DM9102H interfaces to the UTP3, 4, 5 in 10Base-Tand the UTP5 in 100Base-TX. It is fully compliant with theIEEE 802.3u Spec. Its auto-negotiation function willautomatically configure the DM9102H to take the maximumadvantage of its abilities. The DM9102H also supports IEEE802.3x's full-duplex flow control.The DM9102H supports two types of power managementmechanisms. The main mechanism is based on the OnNow architecture, which is required for PC99. Thealternative mechanism is based upon the remoteWake-On-LAN mechanism.

128-pin LQFP

Integrated Fast Ethernet MAC, Physical Layer and Transceiver in one chip, Comply with PCI specification 2.2, PCI clock up to 66MHz, PCI bus master architecture, PCI bus burst mode data transfer, Two large independent transmission and receipt of FIFO, Support transmit threshold under-run re-try mode, Up to 256K bytes Boot EPROM or Flash interface, EEPROM 93C46 interface automatically supports node ID load and configuration information, Comply with IEEE 802.3u 100Base-TX and 802.3 10Base-T, Comply with IEEE 802.3u auto-negotiation protocol for automatic link type selection, Support IEEE 802.3x Full Duplex Flow Control, VLAN frame length support, IP/TCP/UDP checksum generation and checking, Comply with ACPI and PCI Bus Power Management, Support the MII (Media Independent Interface) for an external PHY, Support Wake-On-LAN function and remote wake-up (Magic packet, Link Change and Microsoft wake-up frame), Support 4 Wake-On-LAN (WOL) signals (active high pulse, active low pulse, and active high, active low,), High performance 100Mbps clock generator and data recovery circuit, Digital clock recovery circuit, using advanced digital algorithm to reduce jitter, Provides Loopback mode for easy system diagnostics, Support auto-MDIX, +1.8/3.3V Power supply with +5V tolerant I/O, 128 pin LQFP with CMOS process.